1. Field of the Invention
Method of manufacturing integrated circuits by means of a multilayer mask and device obtained by means of the said method.
The invention relates to a method of manufacturing a semiconductor device having a semiconductor body which is provided at a surface with a transistor having an emitter region and a collector region of the first conductivity type and an intermediately located base region of the second conductivity type, in which a mask having at least two sublayers, a first or bottom layer and a second layer formed on it and which can be etched selectively with respect to each other, is provided on the surface, which mask comprises a first mask portion which covers the region of the emitter and a region of an extrinsic portion of the base at the circumference of the emitter and which is bounded by an aperture in which via said aperture a zone of the second conductivity type is formed in the semiconductor body and the bottom layer is subjected to a selective etching treatment in which by lateral etching an edge of the bottom layer of the first mask portion is removed, after which, via the thus exposed part of the surface, an impurity of the second type is again introduced into the semiconductor body to form the extrinsic portion of the base, and in which at the areas where the second layer and the bottom layer have been removed, an insulating layer is formed of a material with respect to which the layers of the first mask portion can be etched selectively, in which the first mask portion can then be removed entirely and the emitter and the intrinsic portion of the base are then formed via the thus obtained aperture.
2. Description of the Prior Art
It is known that the properties of semiconductor devices are dependent on the shape and the dimensions of the various elements formed in the semiconductor material. In order to improve the behaviour of said devices at very high frequencies, it is endeavoured to reduce the dimensions and to increase the accuracy in the localisations of the regions.
A metehod of the above-mentioned kind is known inter alia from U.S. Pat. No. 3,940,288. In this known method a mask is used having three layers which are situated one on top of the other and which consist alternately of silicon oxide and silicon nitride. In this manner it is possible to obtain, in addition to an emitter of very small dimensions, a base of a low base resistance r.sub.bb. However, it is not possible by means of the same method to obtain a simultaneous self-alignment of the base contact aperture, the emitter contact aperture and the collector contact aperture and, possible, of the insulation zones so that it would be possible to provide said apertures at a minimum distance from each other without taking into account the alignment tolerances of successive masks.